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Advance Information
NTSC Digital Video Encoder
HCMOS Technology
The MC44722 and MC44723 are Digital Video Encoders (DVE). They convert ITU-601/656 standard 4:2:2 Bit-Paralellel data into analog composite video, S-Video or Y/Cb/Cr in PAL and NTSC formats. They accept the multiplexed ((CB,Y,CR)Y) signals from digital sources such as MPEG decoders and can act as a sync generator master. All video processing is done digitally and requires no external adjustment. Specifically designed for digital satellite, digital cable decoders and multimedia terminals.
MC44722 MC44723
* World Wide Operation (PAL-BDGHI, PAL-N,PAL-M, NTSC-M) * SMPTE 170M / ITU - R 624 composite video output * Programmable Color Sub-carrier Frequencies * Analog Horizontal, Vertical, Frame or Composite Sync Outputs * Sync Extraction From Digital Input Data (SAV, EAV) * Sync Polarity and Horizontal Phase Control * Master or Slave Sync (H/Vsync, H/Fsync, ITU-R656 slave) Operation * Interlaced or Non-Interlaced Support * 625/50 or 525/60 ITU-601/656 8-bit ((CB,Y,CR)Y) Digital Input * Luma 2X / Chroma 4X Oversampling Filtering * External VBI Information Data Input (such as TeleText Information Data) * CVBS / YS / CS or Y / Cb / Cr Analog Outputs Through 10-bit DACs * Easily programmed via Serial Bus ( I2C or SPI Bus) * 2 Hardware I2C Chip Addresses * Closed-Caption and CGMS Information data Insertion * MACROVISION ver. 7.01 Anti-Copy Signal Insertion (MC44722 Only support NTSC mode) * On Chip Color - bar Generator * +3.3V Power Supply or +3.3V(Digital)/+5V(Analog) Power Supply * Pin Compatible with MC44720FT
FT SUFFIX 48 QFP (0.8mm Pitch)
The MC44722 device is protected by U.S. patent number 4,631,603,4,577,216 and 4,819,098 and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
No. 1
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Pin Assignment]
43
48
42
47
41
46
40
45
39
44
38 TP8
DVdd
DVss
TP0
TP1
TP7
TP2
TP3
TP4
TP5
1 2 3 4 5 6 7 8 9 10 11 12
CVBS / Cb CVBS / Cb CVBS/CbVdd Y Y YVdd C / Cr C / Cr CVdd DAVss Ibias PAL/NTSC DAVdd ChipA SDA/SI SCL/SCK VReff TEST DVdd DVss clock Reset
TP6
TP9 Hsync F / Vsync EXT TVIN DVIN0
37
36 35 34 33 32 31 30 29 28 27 26 25
MC44722 MC44723
DVIN1 DVIN2 DVIN3 DVIN4 DVIN5 DVIN6 DVIN7
18
13
19
SEL
SO
14
20
15
21
16
22
17
23
No. 2
24
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Pin Descriptions]
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25~32 33 34 35 36 37 38 39~41 42 43 44~48 NAME CVBS / Cb CVBS /Cb CVBS/CbVdd Y Y YVdd C/Cr C/Cr C/CrVdd DAVss Ibias DAVdd VReff ChipA TEST SO SDA/SI SCL/SCK SEL DVss CLOCK DVdd Reset PAL/NTSC DVIN7~0 TVIN EXT F/Vsync Hsync TP9 TP8 TP7~5 DVss DVdd TP4~0 I/O O O O O O O O DESCRIPTIONS Analog composite video signal output or Cb signal output current drive(positive) Analog composite video signal output or Cb signal output current drive(negative) Power Supply for CVBS / Cb DAC circuit Analog luminance signal output current drive(positive) Analog luminance signal output current drive(negative) Power Supply for Y DAC circuit Analog chrominance signal output or Cr signal output current drive(positive) Analog chrominance signal output or Cr signal output current drive(negative) Power Supply for C / Cr DAC circuit Ground for DAC circuit Reference current for the 3 DACs Power Supply for DAC circuit Reference full scale voltage for the 3 DACs I2C chip address select { 0 : 42(hex)/43(hex) 1 : 1C(hex )/1D(hex) } TEST pin(Ground) If SPI mode, serial data output / If I2C mode, connect to Ground Serial data input, Open drain output / If SPI mode, serial data input Serial clock Connect to Ground / If SPI mode, this pin is chip select Ground for Digital circuit 27MHz clock input Power Supply for Digital circuit Reset signal, active LOW NTSC/PAL select . This pin active only Reset time. (NTSC : Low PAL : High ) 8-bit Multiplexed Y/Cr/Cb 4:2:2 data(CCIR Rec656) input(1) TEST data input Csync/Frame sync output or external VBI information input Frame sync or Vertical sync input/output Horizontal sync input/output for D/A converter test MUX switch in 8-bit Multiplexed Y/Cr/Cb 4:2:2 data(CCIR Rec656) input mode, or Test data input/output 8-bit Multiplexed 4:2:2 data(CCIR Rec656/601) input(2), or Multiplexed Cr/Cb data (CCIR Rec656/601) input in 16-bit input mode (MSB : TP7), or Test data input/output Ground for Digital circuit Power Supply for Digital circuit 8-bit Multiplexed 4:2:2 data(CCIR Rec656/601) input(2), or Multiplexed Cr/Cb data (CCIR Rec656/601) input in 16-bit input mode (LSB : TP0), or Test data input/output
I z(O) I/O(I) I (I) I I I I I I/O I/O I/O I/O I/O I/O
I/O
No. 3
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Block Diagram]
F/Vsync
ChipA DVdd DVdd DVss DVss
CGMS_gen CC_gen 0
EXT
Hsync
YVdd
Sync_generator
BG
copy protection
bus
CVBS/CbVdd C/CrVdd DAC YOUT YOUT CVBSOUT / Cb CVBSOUT / Cb COUT / Cr COUT / Cr VReff Ibias DAVdd DAVss
H,V
0 demux 0 Modulator 0 0 0
TP0~7
Cb
TVIN clock Reset PAL/NTSC
Cr
subcarrier gen
I2C / SPI
TEST
MC44722/3
SO SEL SCL/SCK SDA/SI TP0~9 TEST
I2C/SPI chip-address
42/43(hex) 1C/1D(hex)
No. 4
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
BIAS
DAC
DAC
DVIN
Y
0
off_set
[Function Descriptions]
Clock
27.0Mhz is necessary. This signal on the clock pin needs to be active before the reset pin is de-asserted. ( see figures 1 and 2 )
Reset Procedure
RESET is a level sensitive input pin. Driving the RESET pin low causes a DVE reset. The 27Mhz DVE clock signal must be active before RESET is released. De-asserting reset will latch the status of the PAL/ NTSC, TVIN and SEL pins. The PAL/NTSC pin determines the default values for the DVE control registers. The default register values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately when a valid input digital video data stream is present. The value on the SEL pins determine the default serial communication mode. If Low, the DVE use I2C bus operation. If High, the DVE use 4-wire SPI operation. After reset, the VBI signals (Closed-Caption and CGMS) are disabled. (see page --- for sub-address register descriptions.)
Fig 1 : DVIN Data Input Timing
Input Clock 27MHz
50% Tds
Input Data DVIN0~7 Tdh
Fig 2 : Sync Data Output Timing
Clock 27MHz Output Data TP0~8 Output data H/VF sync Td Td
No. 5
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Input Data Format
The input digital video is in accord with the ITU-R Rec.656 and SMPTE 125M standards. It is two 8-bit or 16-bit multiplexed 4:2:2 ((CB,Y,CR)Y) data stream. Samples are latched on the rising edge of the clock signal. Data is input on pins DVIN[ 7 : 0 ] and TP[ 8 : 1 ] (see figures 3 and 4 for sub-address register descriptions.)
Video Timing / Sync Generator
The DVE outputs PAL-B,D,G,H,I, PAL-N, PAL-M or NTSC-M standard video signals. The DVE sync generator can be operated in two modes, master or slave. In master mode, the DVE generates all the correct Horizontal and Vertical or Frame sync signals internally, or it is output Csync signal through the EXT pin(C/Fsync). In slave mode, the DVE derives the sync signals from the Bit-Parallel input data stream Start Active Video (SAV) and End Active Video (EAV) data packet information. Sync signals are output on the Hsync and F/Vsync or EXT pins and can be programmed for positive or negative polarity. The phase of Hsync can also be controlled. Also, the DVE allows more two slave modes. One is H/Vsync slave, and the aother is H/Fsync slave mode. Vertical Blanking corresponds to the following lines. 625/50 624-22 311-335 ITU-R line numbering 525/60 1-19 264-282 SMPTE line numbering (see figures 3,4,5,6,7,8,9,10, and 11 for sub-address register descriptions.)
Fig 3 : Digital Input Timing(525/60 system) in Master Mode
Hsync phase sub-address71[2:0] +3T delay
70(hex){[1:0]=01}
-4T delay Hsync
Hsync polarity sub-address71[5]
T clock
124T
242T
1440T
8-bit input mode
DVIN0~7 INVALID
FF 00 00 XY Cb0 Y0 Cr0 Y1 Cb2 Y2 Cb718 Y718 Cr718 Y719 FF 00 00
16-bit input mode
DVIN0~7 INVALID TP0~7 INVALID
or Cr0 Cb0 Cb0 Cr0 Cb2 Cr2 Cb718 Cr718 Cr718 Cb718 Y0 Y1 Y2 Y718 Y719
No. 6
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 4 : Digital Input Timing(625/50 system) in Master Mode
Hsync phase sub-address71[2:0] +3T delay
70(hex){[1:0]=01}
-4T delay Hsync
Hsync polarity sub-address71[5]
T clock
124T
262T
1440T
8-bit input mode
DVIN0~7 INVALID
FF 00 00 XY Cb0 Y0 Cr0 Y1 Cb2 Y2 Cb718 Y718 Cr718 Y719 FF 00 00
16-bit input mode
DVIN0~7 INVALID TP0~7 INVALID
or Cr0 Cb0 Cr2 Cr718 Cb718 Cb0 Cr0 Cb2 Cb718 Cr718 Y0 Y1 Y2 Y718 Y719
Fig 5 : Sync Timing::525/60 Interlaced System in Master Mode
Fsync polarity sub-address71[3]
sub-address71[7] =0
Fsync Vsync
Vsync polarity sub-address71[4]
Hsync CSYNC 524 525 1 2 3 4 5 6 7 8 9 10 11 21 22 23
Fsync Vsync Hsync CSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 283 284 285
No. 7
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 6 : Sync Timing::625/50 Interlaced System in Master Mode
Fsync polarity sub-address71[3] Vsync polarity sub-address71[4]
sub-address71[7] =0
Fsync Vsync Hsync CSYNC 621 622 623 624 625
1
2
3
4
5
6
7
8
9
21
22
23
Fsync Vsync Hsync CSYNC 309 310 311 312 313 314 315 316 317 318 319 320 321 334 335
Fig 7 : Sync Timing::525/60 Non-interlaced System in Master Mode
Fsync polarity sub-address71[3]
sub-address71[7] =1
Fsync Vsync
Vsync polarity sub-address71[4]
Hsync CSYNC 261 262 1 2 3 4 5 6 7 8 9 10 11 21 22 23
Fig 8 : Sync Timing::625/50 Non-interlaced System in Master Mode
Fsync polarity sub-address71[3] Vsync polarity sub-address71[4]
sub-address71[7] =1
Fsync Vsync Hsync CSYNC 308 309 310 311 312
1
2
3
4
5
6
7
8
9
21
22
23
No. 8
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 9 : Analog Sync Timing::Rise and fall
0.148uS 2.37uS 29.41uS 63.56uS 27.04uS
0.148uS 4.74uS
NTSC
0.222uS 2.37uS 29.63uS 64.00uS 27.26uS
0.222uS 4.74uS
PAL
Fig 10 : Sync Timing::525/60 Interlaced System in Slave Mode Odd field
Fsync Vsync Fsync polarity sub-address71[4]
sub-address71[1:0] =10, 11
Vsync polarity sub-address71[5]
Hsync
Internal Hsync reset counter
Hsync Delay sub-address 7A[7:0], 71[3:0]
CSYNC 3 4 5 6 7
Even field
Fsync Vsync Hsync CSYNC 266 267 268 269
No. 9
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 11 : Sync Timing::625/50 Interlaced System in Slave Mode
sub-address71[1:0] =10, 11
Odd field
Fsync Vsync
Fsync polarity sub-address71[4]
Vsync polarity sub-address71[5]
Hsync
Internal Hsync reset counter
Hsync Delay sub-address 7A[7:0], 71[3:0]
CSYNC 625 1 2 3 4
Even field
Fsync Vsync Hsync CSYNC 313 314 315 316
No. 10
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Chroma / Luma Encoding
The DVE de-multiplexes the 4:2:2 digital video data stream. The de-multiplexed Y or Luma samples are interpolated (2X oversampled) at the clock rate. Offset compensation is then added, next any VBI signals consisting of Closed-Caption and VID are added to the appropriate lines, then finally composite sync pulses are added to the Luma signal. (see figure 12.) De-multiplexed component color CB and CR samples are interpolated (4X oversampled) at the clock rate. Interpolating simplifies the output filter and allows more accurate encoding. The DVE generates the necessary subcarrier color frequency for PAL or NTSC encoding from the 27Mhz system clock. This color subcarrier is then modulated by the base band component color CB and CR signals to create the video Chroma signal. (see figure 13.) A 7.5 IRE pedestal is added for the 60Hz field rate. This can be added for the 50Hz field rate through serial bus control. (see sub-address register descriptions)
CVBS and S-VIDEO or YCbCr Outputs
The internal digital video signals drive 10-bit D/A converters. Converter outputs are bi-directional current sources where the current is proportional to the digital data with reference to the IBIAS reference current. The pins CVBS/Cb, Y and C/Cr are the respective composite, Luma and Chroma or Y/Cb/Cr signal current source pins. Also, each DACs can drive 75ohm load register. (see "Application Diagram" and "sub-address register descriptions".) Bias Current Gain
DACs can be switched off through serial bus control to reduce power consumption. Both outputs of unused DACs should be connected to ground through a resister to avoid charge buildup.
No. 11
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 12 : Luminance Output Range
470 420 340 290 212 162 82 32 32
Digital Y input code(16~235) 525/60 and 625/50 system 100%amplitude,100%saturation color bar
IRE 100 89 70 59 41 30 11 0 200 232 670 620 540 490 412 362 282 232
code 1023
-40
12
Analog Y output level(525/60 system) 100%amplitude,100%saturation color bar
0
IRE 100 89 70 59 41 30 11 0 232 670 620 540 490 412 362 282 232
code 1023
-43
44
Analog Y output level(625/50 system) 100%amplitude,100%saturation color bar
0
No. 12
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 13 : Chrominance Output Range
480 444 332 292 256 220 68 32 32 108 256 256 180 256 404 480
Digital Cr-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar
Digital Cb-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar
IRE A }30 A }32 A }30 A }32 A }22 A }22 A }11
code 1023
63 59 45 20 0 -20 -45 -59 -63
511
0
Analog C output level(525/60 system) 100%amplitude,100%saturation color bar
IRE A }30 A }32 A }30 A }32 A }22 A }22 A }11
code 1023
67 63 48 21.5 0 -21.5 -48 -63 -67
511
0
Analog C output level(625/50 system) 100%amplitude,100%saturation color bar
No. 13
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Copy Generation Managment System (CGMS) Encoding
CGMS signals can be encoded by the DVE onto output video line 20 (525 / 60 for Japan). CGMS identification signals also identify and control the TV screen presentation mode - wide screen, letterbox and or normal -16:9 or 4:3. (see figures 16 for sub-address register descriptions.)
Closed-Caption Encoding
Closed-Captioned or Extended Data Service signals can be encoded by the DVE onto output video line 21/284 (NTSC) and line 22/335 (PAL). The CC data is input through the serial bus interface. Two 8-bit byte data pairs are encoded for each field. There are four registers for holding the data - two bytes per field. The serial data is 7bit US-ASCII MSB first, proceeded by an odd parity bit. Total 8-bits. (P-7-6-5-4-3-2-1-0) The DVE automatically generates the required clock run in and start bit for CC encoding. (see figure 16.) When Closed-Captioning is enabled, the system micro processor (uP) should update the CC data once each frame. The system uP should also write NULL characters when there is no CC data to encode. It is also recommended to write CC data only to the inactive frame. Field1 and Field2 data are double-buffered by the Frame sync falling edge of previous Frame, updating Frame 2 data during Frame1 display and Frame1 data during Frame2 display. (see figures 18 for sub-address register descriptions.)
No. 14
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Serial Control Bus
Control of the DVE device is accomplished through the I2C-Bus or SPI serial bus. In I2C mode, pins SDA and SCL are the respective data and clock signals. Device address can be 42(hex)/43(hex) or 1C(hex)/1D(hex) . Slave address is chosen at reset by the state of the ChipA pin signal { 0 : 42(hex)/43(hex), 1 : 1C(hex)/1D(hex) } Sub-address register read and write operations are documented in the following section. In SPI mode, pins SO, SI, SCK and SEL are the respective data input, output, serial clock and chip select signals. Register read and write operations are documented in the following section.
MACROVISIONTM Copy Protection
When the MC44722 is enabled this features in NTSC mode, the Luma and Chroma signals are modified according to the MACROVISIONTM copy protection process for Pay Per View (PPV) applications revision 7.01 dated Sep 6th , 1996. But this feature is NOT supported in PAL mode, so please do NOT use this features in PAL mode. Enabling and control is through the serial control bus. No parts will be sent to the customer until the customer provides MOTOROLA with written confirmation of a license, non-disclosure or waiver from MACROVISIONTM. If your customer does NOT use this features, please recommend to use the MC44723 no-supported the copy-guard features.
No. 15
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 14-a : I2C-BUS Interface Write operation Timing
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Start
chip address(write)
ACK
Sub-address
ACK
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Data 1
ACK
Data N
ACK
Stop
Fig 14-b : I2C-BUS Interface Read operation Timing
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Start
chip address(write)
ACK
Sub-address
ACK
Stop
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Start
chip address(Read)
ACK
Data 1
ACK by MCU
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Data 2
ACK by MCU
Data N
Stop ACK by MCU
No. 16
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This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 15-a : SPI-BUS Interface Write operation Timing
SEL
SCK
SI
x
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
SO (Don't care)
x
x MSB
x
x
x
x
x
x
x LSB
x MSB
x
x
x
x
x
x
x LSB
Start
Write Command
Sub-address
SEL SCK
SI
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
SO (Don't care)
D7 x MSB
x
x
x
x
x
x LSB
x MSB
x
x
x
x
x
x
x LSB
Data 1
Data N
No. 17
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This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 15-b : SPI-BUS Interface Read operation Timing
SEL
SCK
SI SO (Don't care)
x
D7 D6 MSB x MSB x
D5
D4
D3
D2
D1
D0 LSB x LSB
D7 D6 MSB x MSB x
D5
D4
D3
D2
D1
D0 LSB x LSB
x
x
x
x
x
x
x
x
x
x
x
Start
Write Command
Sub-address
Stop
SEL
SCK
SI
x
D7 D6 MSB x MSB x
D5
D4
D3
D2
D1
D0 LSB x LSB
x MSB
x
x
x
x
x
x
x LSB D0 LSB
SO
x
x
x
x
x
x
D7 D6 MSB
D5
D4
D3
D2
D1
Start
Read Command
Data 1
SEL
SCK
SI
x MSB
x
x
x
x
x
x
x LSB D0 LSB
x MSB
x
x
x
x
x
x
x LSB D0 LSB
SO
D7 D6 MSB
D5
D4
D3
D2
D1
D7 D6 MSB
D5
D4
D3
D2
D1
Data 2
Data N
Stop
No. 18
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Specifications]
Maximum Ratings DC Supply Voltage Input Voltage, All Inputs Output Voltage, All Outputs DC Output Current, per Pin Power Dissipation Storage Temperature Vdd Vin Vout Iout Pd Tstg -0.5 ~ +7.0 -1.5 ~ Vdd+1.5 -0.5 ~ Vdd+1.5 25 750 -65 ~ +150 V V V mA mW Ae
Electrical Characteristics Characteristic Power Supply Voltage(Analog Blocks) DAVDD Power Supply Voltage(Digital Blocks) DVDD Supply Current(Analog Blocks) Supply Current(Digital Blocks) Operating Temperature
Symbol Min AVDD 3.1 4.75 DVDD 3.1 AIcc DIcc Ta 0
Typ 3.3 5.0 3.3 30 170 -
Max 3.5 5.25 3.5 70
Unit V V mA mA Ae
DAC Blocks Characteristics(Power Supply 3.3V,Ta=25A e A }3A e ) Characteristics Symbol Min Typ Max Resolution 10 Integral Non-Linearity INL A }4.0 Differential Non-Linearity DNL A }2.0 Analog Output Voltage Vyo 0.85 1.00 1.15 Full Scale Output Voltage Vyfs 0.85 1.00 1.15 Zero Scale Output Voltage Vyzs 0.0 0.1 External Load Resistance RL 75 120 -
Unit Bit LSB LSB Vp-p V V E
Other Vref = 1.1V Vref = 1.1V Vref = 1.5V
DAC Blocks Characteristics(Power Supply 5.0V,Ta=25A e A }3A e ) Characteristics Symbol Min Typ Max Resolution 10 Integral Non-Linearity INL A }4.0 Differential Non-Linearity DNL A }2.0 Analog Output Voltage Vyo 1.5 2.0 Full Scale Output Voltage Vyfs 1.5 2.0 Zero Scale Output Voltage Vyzs 0.0 0.1 External Load Resistance RL 75 240 -
Unit Bit LSB LSB Vp-p V V E
Other Vref = 1.5V Vref = 1.5V Vref = 2V Vref = 2V
No. 19
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This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Specifications]
Clock Blocks Characteristics Characteristic Clock Rate Clock Duty Cycle
Symbol fc Dty
Min 40
Typ 27.0 50
Max 60
Unit MHz Ai
Digital Blocks Electrical Characteristics(Power Supply 3.3V,Ta=25A Characteristics Symbol Min Typ Input Voltage HIGH ViH 2.0 LOW ViL Output Voltage HIGH VoH 2.4 (2.0mA) LOW VoL Input Leakage Current Iin A }2.5 Hi-Z Leakage Current Ioz A }20 Input Capacitance Cin Load Capacitance CL Data Setup Time Tds 4 Data Hold Time Tdh 5 Input Rise Time Tr Input Fall Time Tf Data delay Td -
e A }3A e ) Max Unit V 0.8 V V 0.5 V EA EA 20 pF 20 pF nS nS 5 nS 5 nS 27 nS
IIC/SPI-BUS Blocks Characteristics(Power Supply 3.3V,Ta=25A e A }3A e Characteristics Symbol A @Min Typ Input Voltage LOW VILM 0.8 Input Voltage High VIHM 2.3 Input Current VIM A }10 SDA Output Voltage (IOM=3mA) VOM 0.4 Output Current (during acknowledge) IOM 3 -
) Max Unit V V EA V mA
Clock
50A
50A
Tds Input Data not valid
Tdh not valid
Tr
Tf
valid
No. 20
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[I2C-BUS Slave Address 42(hex)/43(hex) or 1C(hex)/1D(hex)]

WRITE MODE
S Slave Address
A
Sub Address
A
DATA 0
A
--------
DATA N
AP
42(hex) or 1C(hex) if more than 1byte DATA is transmitted, then auto-increment of the Sub Address is performed
S Slave Address A Sub Address DATA 0 DATA N P
Start condition 42(hex) or 1C(hex) Acknowledge, generated by the slave Sub address byte First data byte continued data byte(Sub Address is auto increment) Stop condition
READ MODE
S
Slave Address
A
Sub Address N
AP
Slave receiver
42(hex) or 1C(hex) then S Slave Address A DATA N AM DATA N + 1 AM --------- AM P Slave transmitter
43(hex) or 1D(hex)
S Slave Address A Sub Address N DATA N DATA N + 1 AM P
Start condition Slave receiver is act transmitter is ad Acknowledge, generated by the slave Sub Address byte DATA byte of Register N DATA byte of Register N + 1 (address auto-increment) Acknowledge, generated by the micro controller Stop condition (When Last AM must be '1' )
No. 21
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[SPI-BUS]

WRITE MODE
S
Write Command 42(hex) or 1C(hex)
Sub Address
DATA 0
--------
DATA N
P
if more than 1byte DATA is transmitted, then auto-increment of the Sub Address is performed
S Write Command Sub Address DATA 0 DATA N P
Chip select on ( Hi to Lo) 42(hex) or 1C(hex) Sub address byte First data byte continued data byte(Sub Address is auto increment) Chip select off (Lo to Hi)
READ MODE
S
Write Command 42(hex) or 1C(hex)
Sub Address N
P
Slave receiver
then S Read Command 43(hex) or 1D(hex) DATA N DATA N + 1 --------P Slave transmitter
S Sub Address N Read Command DATA N DATA N + 1 P
Chip select on (Hi to Lo) Sub Address byte set 43(hex) or 1D(hex) DATA byte of Register N DATA byte of Register N + 1 (address auto-increment) Chip select off (Lo to Hi)
No. 22
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Register Mapping and Description]
Sub-address 70 : Variable I/O Switch (write/read) MSB Register 70 bs-off self-SW
color bar select VBLK SW
EXTsync SW F/Vsync SW M/S mode1
LSB
M/S mode0
default : 0000_0001(bin)
bs - off
: color burst control switch On/Off 0 : color burst ON (default) 1 : color burst OFF : internal self H/V counter reset switch On / Off 0 : self counter reset OFF (default) 1 : self counter reset ON Note : this mode is ONLY valid at when 70h[1: 0] is "10(bin)" or "11(bin)". : color bar select 0 : color bar 1 : color bar Luma 100% 100% Chroma 100% 75%
self - SW
color bar select
VBLK SW
: Vertical Blanking Mask Enabale switch On-Off 0 : reject VBI information data in vertical blanking period (default) 1 : through VBI information data in vertical blanking period : Composite sync/Flame sync output switch 0 : Frame sync output (default) 1 : compsite sync output : Flame sync /Vertical sync output switch 0 : Vertical sync output (default) 1 : Frame sync output
EXTsync SW
F/Vsync SW
M/S sync mode1 : Master or Slave sync mode M/S sync mode0 00 : 656 slave or H/V master mode 01 : 656 slave mode(no H/Vsync output) (defalt) 10 : Fsync/Hsync slave mode 11 : Vsync/Hsync slave mode
No. 23
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 71 : Sync control (write/read)
MSB Register 71 non-inter VBI SW h-polarity v-polarity f-polarity h- delay2 h-delay1
LSB h-delay0
default : 0000_0100(bin)
non-inter
: non-interlaced mode select 0 : interlace mode (default) 1 : non-interlace mode : vertical blanking information signal input control switch on EXT pin 0 : VBI input Off (default) 1 : VBI input On : polarity of Hsync 0 : negative (default) 1 : positive : polarity of Vsync 0 : negative (default) 1 : positive : polarity of Fsync 0 : field1 (odd) = low level (default) 1 : field1 (odd) = high level : delay on Hsync with referance to DVIN data in Master mode 000: + 4 clock delay 001: + 3 clock delay 010: + 2 clock delay 011: + 1 clock delay 100: + 0 clock delay 101: - 1 clock delay 110: - 2 clock delay 111: - 3 clock delay Note : this h-delay can be also related with 7A[7:0] register and can delay totally +2023 clock delay in H/V or H/Fsynnc slave mode.
VBI SW
h-polarity
v-polarity
f-polarity
h-delay2 h-delay1 h-delay0
No. 24
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 72 : PAL/NTSC setup (write / read)
MSB Register 72
phase-set TEST EXT I/O SW
LSB color bar setup75 625/525
PAL/ NTSC2 PAL/ NTSC1
default : 0000_1000(bin) NTSC (If "PAL/NTSC" pin is LOW level) 0000_0101(bin) PAL
phase-set
: color sub-currier phase syncronization 0 : free running (default) 1 : 1 phase reset/8 field and 1 phase reset/4 flam : for test, should be "0" : Input/Output switch on EXT pin 0 : VBI input(default) 1 : Csync or Flame sync output : internal color bar genarator control 0 : nomal operation (default) 1 : color bar genarator On (need to set color bar mode on sub-address 70[5]. ) : Setup level for Luminance 0 : setup level for luminunce = 0IRE 1 : setup level for luminunce = 7.5IRE
TSET EXT I/O SW
color bar
setup75
625/525 : control line mode 0 : 525 lines / 60 Hz mode 1 : 625 lines / 50 Hz mode PAL/NTSC2 PAL/NTSC1 : subcarrier control 00 : NTSC(M) 01 : PAL (BDGHI) 10 : PAL (M) 11 : PAL (N)
No. 25
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 73: Vertical Blanking Information Luma (Y) Level (write only) MSB Register 73 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 LSB
default : 1000_0000(bin)
Sub-address 74: Vertical Blanking Information Chroma (U) Level (write only)
MSB Register 74 U7 U6 U5 U4 U3 U2 U1 U0
LSB
default : 79(dec) (NTSC) 157(dec) (PAL)
Sub-address 75: Vertical Blanking Information Chroma (V) Level (write only)
MSB Register 75 V7 V6 V5 V4 V3 V2 V1 V0
LSB
default : 128(dec) (NTSC) 107(dec) (PAL)
No. 26
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 76 : signal control 1(write only) MSB Register 76 Cr Cb Luma CVBS dac C dac
Y dac
LSB dac sw1 dac sw0
default : 0000_0000(bin)
Cr Cb Luma
: Cr/Cb signal control 0 : Cr, Cb On (default) 1 : chrominance Off : luminance control 0 : luminance On (default) 1 : luminance Off : D/A converter output On-Off control 0 : CVBS/CbDAC, C/CrDAC, YDAC output On (default) 1 : CVBS/CbDAC, C/CrDAC, YDAC output Off : 1~9-pin's D/A converter output signal control 10 : Y/Cr/Cb output On 00 : Y/C/CVBS output On
CVBSdac Cdac Ydac dac sw1 dac sw0
Sub-address 77 : signal control 2 (write only ) MSB Register 77 dac sw4 LSB dac sw3
default : 0000_0001(bin)
dac sw4 dac sw3
: D/A converter output signal control 10 : Y/Cr/Cb output On 00 : Y/C/CVBS output On
No. 27
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 78~79 : Sub-carrier phase control (write only) MSB Register 78 sc-ph9 sc-ph8 sc-ph7 sc-ph6 sc-ph5 sc-ph4 sc-ph3 LSB sc-ph2
default : 0000_0000(bin)
MSB Register 79 sc-ph1
LSB sc-ph0
default : 0000_0000(bin)
sc-ph9 sc-ph8 sc-ph7 sc-ph6 sc-ph5 sc-ph4 sc-ph3 sc-ph2 sc-ph1 sc-ph0
: sub-currier phase control 0000_0000 : sub-currier phase 0 degree (default) to 1111_1111 : sub-currier phase 359 degree
Sub-address 7A : Hsync delay control (write only) MSB LSB Register 7A H-dela10 H-delay9 H-delay8 H-delay7 H-delay6 H-delay5 H-delay4 H-delay3
default : 0000_0000(bin)
h-delay10 h-delay9 h-delay8 h-delay7 h-delay6 h-delay5 h-delay4 h-delay3
: delay on Hsync with reference to DVIN data 0000_0000_000 : Hsync delay 0 delay to 1111_1111_000 : Hsync delay +255 delay
Note : this h-delay can be also related with 71[3:0] register and can delay totally +2023 delay(1111_1111_111) in H/V or H/ Fsync slave mode.
No. 28
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 7B : Digital Video Input Select Control (write only) MSB Register 7B Cr_tmg 2 Cr_tmg1 Cb_tmg 2 Cb_tmg1 Y_tmg
LSB
16-bit input mode
default : 0000_0000(bin)
Cr/Cb_tmg2 Cr/Cb_tmg1
: Cr/Cb clock timing delay in 16-bit Digital Input Mode 00 : Cr clock delay 0 clock (default) 01 : Cr clock delay +1 clock 10 : Cr clock delay +2 clock 11 : Cr clock delay +3 clock : Y clock timing delay in 16-bit Digital Input Mode 0 : Y clock delay 0 clock (default) 1 : Y clock delay +1 clock : 16-bit Multiplexed CbYCrY Digital Video Inout mode 0 : 8-bit CbYCrY Digital Video Input mode (default) 1 : 16-bit CbYCrY Digital Video Input mode
Y_tmg
16-bit input mode
No. 29
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 80~82: CGMS characters for Field1(Line20)/Field2(Line283) (write only) MSB Register 80 MSB Register 81 MSB Register 82 XX XX XX XX vid134 b20 vid133 b19 vid128 b16 vid127 b15 vid126 b14 vid125 b13 vid124 b12 vid123 b11 vid118 b8 vid117 b7 vid116 b6 vid115 b5 vid114 b4 vid113 b3
NTSC only LSB vid112 b2 vid122 b10 vid132 b18 vid111 b1 LSB vid121 b9 LSB vid131 b17
49.1A }0.5E 11.2A }0.6E 70IRE 2.235E
0IRE
Ref
b1 b2 b3 b4 b5 b6 b7 b8 b9 b10
b12 b14 b16 b18 b20 b11 b13 b15 b17 b19
-40IRE
Fig 16 : CGMS wave form
No. 30
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 83~84 :closed caption characters/extended data for Field1(Line21) (write only) default 1000_0000 First byte to Encode MSB Register 83 ccp118 ccb117 b7 ccb116 b6 ccb115 b5 ccb114 b4 ccb113 b3 ccb112 b2 ccb111 b1 LSB ccb127 b7 ccb126 b6 ccb125 b5 ccb124 b4 ccb123 b3 ccb122 b2 ccb121 b1 parity Second byte to Encode MSB Register 84 ccp128 parity LSB
Sub-address 85~86 :closed cation character/extended data for Field2(Line284) First byte to Encode MSB Register 85 ccp218 ccb217 b7 ccb216 b6 ccb215 b5 ccb214 b4 ccb213 b3 ccb212 b2
LSB ccb211 b1 LSB ccb227 b7 ccb226 b6 ccb225 b5 ccb224 b4 ccb223 b3 ccb222 b2 ccb221 b1
parity Second byte to Encode MSB Register 86 ccp228 parity
4.15A }0.1E 10.50A }0.5E 12.91E 50IRE 33.764E 50IRE
0IRE
-40IRE
bbbbbbbp bbbbbbb 1234567a 1234567 CHARACTER1 r CHARACTER2 i t y
p a r i t y
0IRE
Fig 17 : Closed caption wave form
sub-address 83 & 84 and 85 & 86 (previous frame data) are double-buffered by Flame sync falling edge
Fsync
Field 1
Field 2
Fig 18 : Closed caption data update timing
No. 31
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 87 :Closed caption/CGMS
MSB Register 87 default 000 VBI : CGMS information data insertion On-Off 0 : CGMS information data insertion Off 1 : CGMS information data insertion On : closed caption/extended data for field2 encoding On-Off 0 : closed caption/extended data for field2 encoding Off 1 : closed caption/extended data for field2 encoding On : closed caption/extended data for field1 encoding 0 : closed caption/extended data for field1 encoding Off 1 : closed caption/extended data for field1 encoding On VBI CC2 CC1
LSB
CC2
CC1
No. 32
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
ChipA DVdd DVdd DVss DVss
EXT
Hsync
device-address 42, 43(hex) or 1C, 1D(hex)
F/Vsync
$71-4
$71-5
$71-6 $71-2,1,0 : H_ phase BG $7A-7,6,5,4,3,2,1,0 $71-7 CC_gen $83~86 $87-1,0
YVdd
copy protection
bus
Sync_gen
VID_gen $80~82 $87-3 $76-5 H,V Y 0 $76-7
CVBSVdd CVdd
0
DAC
YOUT YOUT CVBS/CbOUT CVBS/CbOUT C/CrOUT C/CrOUT VReff Ibias DAVdd DAVss
$76-3 off_set 0 $73-4 0
demux
TP0~7
Cb
0 0 Modulator $74~77 $76-6 $73-5 subcarrier gen $72-1,0
$76-5 $73-6
TVIN clock Reset PAL/NTSC
Cr $71-7 : non_inter/interlaced $72-3 : 625line/525line bus
0
$76-4
I2C / SPI
TEST
MC44722/3
SDA/SI TEST SCL/ SCK SO SEL TP
%% I2C-BUS Slave Receiver Sub-address map %% 77h[7:0] n.a 70h:[7] burst control (default 0:on) 78h[7:0] sub-currier phase control(default 00h) [6] self counter reset switch (default 0:off) 79h[1:0] sub-currier phase control(default 00) [5] color bar select (defalut 0:Luma 100% Chroma 100%) 79h:[7:2] n.a. [4] vertical blanking switch(default 0:off) 7A[7:0] hsync-delay control [3] EXT pin output mode select (Csync:1, Flame sync:0) (In slave mode, is valid with 71h[2:] register) [2] F/Vsync select(default 0:Vsync) 7B[7:6] n.a [1:0] Master/Slave mode select(default 01:656_slave) 7B[5:4] Cr clock timing delay in 16-bit digital input mode 71h:[7] interlaced / non-interlaced 7B[3:2] Cb clock timing delay in 16-bit digital input mode (default 0:interlaced) 7B[1] Y clock timing delay in 16-bit digital input mode [6] VBI input control on EXT pin (default 0:off) 7B[0] 16-bit multiplexed CbYCrY digital input mode [5] horizontal sync polarity (default 0) (default 0: 8-bit multiplexed CbYCrY mode) [4] vertical sync polarity (default 0) 80~82h: Video ID characters for field1(line20)/field2(line283) [3] flame sync polarity (default 0) 83h[7:0] CC character1(line21) (default 'h80) [2:0] hsync delay control (default 100:0 clock delay) 84h[7:0] CC character2(line21) (default 'h80) (In slave mode can use with 7A[7:0]) 85h[7:0] CC character1(line284) (default 'h80) 72h:[7] sub-currier phase syncronaiation(default 0) 86h[7:0] CC character2(line284) (default 'h80) [6] Test mode (default 0:off) 87h[7:3] n.a. [5] EXT I/O switch(defalt 1:cysnc output) [2] CGMS on/off (default 0: off) [4] color bar generate(default 0:off) [1] CC closed caption/extended data for field2 encoding [3] setup level control(default 1:7.5IRE) (default 0: off) [2] 625lines50Hz/525Lines60Hz [0] CC closed caption/extended data for field1 encoding (default set PAL/NTSC pin) (default 0: off) [1:0] PAL/NTSC (default set PAL/NTSC pin) 00:NTSC/M <<<<<<<< M-BUS Format >>>>>> 01:PAL/BGHL ** WRITE MODE ** (10:PAL/M) (11:PAL/N) S | Slave_address(W) | A | Sub_address | A | Data0 | A | ... | DataN | A | P 73h[7:0] Y_register(default 80h) 74h[7:0] 75h[7:0] 76h[7] [6] [5] [4] [3] [2] [1] [0] U_register(default 79d:ntsc/157d:PAL) V_register(default 128d:ntsc/107d:PAL) Cr on/off (default 0:on) Cb on/off (default 0:on) Luma on/off(default 0:on) (default 0: on) CVBS/Cb DAC on/off(default 0: on) C/Cr DAC on/off(default 0: on) C/Cr DAC on/off(default 0: on) CBVS/Y/C Y/Cr/Cb output control swith (default 0 : CBVS/Y/C output) reserved S Slave_address A Sub_address Data0 DataN P Start condition 42(hex) or 1C(hex) Acknowledge generated by me Sub_address register First data Continued data(address is auto incremented) Stop condition
<<<<<<<< SPI-Bus Format >>>>>> ** WRITE MODE ** S | Write Command | Sub_address | Data0 | ... | DataN | P S Write Command Sub_address Data0 DataN P Chip select on (High to Low) 42(hex) or 1C(hex) Sub_address byte First data Continued data byte(address is auto incremented) Chip select off (Low to High)
No. 33
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
BIAS
DAC
DAC
DVIN
[ Apprication Diagram ]
DVdd
47uF 0.01uF
48
47
46
45
44
43
42
41
40
39
38 TP8
TP0
TP1
TP2
TP3
TP4
DVss
CVBS
1
DVdd
TP5
TP6
TP7
TP9 Hsync F/Vsync EXT TVIN DVIN0 DVIN1
CVBS/Cb CVBS/Cb CVBS/CbVdd Y Y YVdd C/Cr C/Cr C/CrVdd DAVss Ibias SCL/SCK DAVdd VReff SDA/SI ChipA TEST SO PAL/NTSC
37
36 35 34 33 32 31 30 29 28 27 26 25
180 Y 0.01uF 47uF 180
2 3 4
180 0.01uF 47uF C 47uF 0.01uF 1.8k 47uF 0.01uF
12 DVdd DVss SEL Reset clock
180
5 6 7
180 180
8 9 10 11
MC44722/3
DVIN2 DVIN3 DVIN4 DVIN5 DVIN6 DVIN7
MPEG DECODE R
13
14
15
16
17
18
19
20
21
22
23
2k 4.7k 1k 0.01uF 47uF 0.01uF 4.7k 100k 10uF 47uF
24
If NTSC system = "0" else PAL system = "1"
0.01uF
MCU
DVdd clock
No. 34
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Package
HD D
Detail A
L1 L c
HE
E
min A A1 A2 b c Detail A A2 D E e HD A1 ZD or ZE e b A HE L L1 E y ZD ZE 13.80 13.80 0.30 0.80 0 1.60 1.60 0.3 0.10 11.90 11.90 0.80 0.05 1.40TYP
max 1.70 0.15
0.45 0.20 12.10 12.10
14.20 14.20 0.70 1.20 10 0.10
unit : mm
No. 35
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E

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